The present invention relates to a semiconductor integrated circuit which selectively supplies a high voltage in response to an input control signal.
An electrically erasable and programmable read only memory (E.sup.2 PROM) which has a floating gate and a control gate to electrically rewrite the stored content has recently prevailed instead of a conventional ultraviolet ray erasable semiconductor memory. The electric rewriting of this memory is executed by injecting electrons to a floating gate by a tunnel effect through an extremely thin oxidized film or by emitting, on the other hand, electrons from the floating gate. A writing voltage higher than a reading voltage, applied at a reading time, is required at the rewriting time utilizing a tunnel current, but, in this case, almost no electric power is consumed. Thus, a voltage-boost circuit (charge pump circuit) is provided in a chip to internally generate a high voltage different from that at the reading time, thereby writing at this high voltage and erasing. Since this necessitates only a sole power source of, for example, 5 volts as an external power source, a user can very readily handle it.
An example of a memory cell of such an E.sup.2 PROM is shown in FIGS. 1A to 1D. FIG. 1A shows a plan view, and FIGS. 1B to 1D are sectional views, respectively, taken along the lines B--B, C--C and D--D in the E.sup.2 PROM shown in FIG. 1A. This E.sup.2 PROM has an n.sup.+ -type drain 2 formed in the surface region of a p-type Si substrate, an n.sup.30 -type source 3 formed in the surface region of a p-type Si substrate, a floating gate 4 formed through a thin gate oxidized film 5 on a channel region, and a control gate 6 formed through a gate oxidized film 7 on the floating gate 4. As shown in FIG. 1D, part of the floating gate 5 is extended through an extremely thin oxidized film 8 on an n.sup.+ -type layer extended from the drain 2 to form a rewriting region.
A principle of the operation of the memory cell is as follows: In the writing operation, the drain 2 and the source 3 are maintained at a zero voltage, a high voltage is applied to the control gate 6 to raise the voltage of the floating gate 4 by capacitive coupling, and electrons from the n.sup.+ -type drain 2 are injected to the floating gate 4 through the extremely thin oxidized film 8 in the rewriting region. In the erase operation, the control gate 6 is maintained at zero voltage, a high voltage is applied to the drain 2, and the electrons of the floating gate 4 are emitted into n.sup.+ -type drain 2. Since the threshold voltage of the memory cell becomes high even if a voltage of 5 volts is, for example, applied as a reading voltage to the control gate 6 in when electrons are injected to the floating gate 4, the memory cell does not turn ON. When the reading voltage of 5 volts is applied to the control gate 6 when the electrons are not stored in the floating gate 4, the memory cell turn ON. Thus, the memory cell selectively stores data "1" or "0".
Such memory cells are arranged in row and column directions in a matrix, the control gates are, for example, commonly connected in the row direction, and the drains and sources are commonly connected in the column direction to compose a memory cell array. In order to produce a high voltage for programming (writing and erasing) by stepping up a power source voltage in a chip, a charge pump circuit as shown in FIG. 2 is, for example, employed.
This charge pump circuit has n stages of step-up section coupled between a load MOSFET QR and an output terminal VO, and a depletion type MOSFET QX coupled between a power source terminal VC and the output terminal VO. Each stage of the step-up section has one of MOSFETs Ql to Qn, and one of capacitors Cl to Cn coupled at one end to the gate and the drain of this MOSFET. A clock pulse .phi.1 shown in FIG. 3(A) is applied to the other terminals of the capacitors in the odd-numbered stages of the step-up sections, and a clock pulse .phi.2 having a predetermined phase difference from the clock pulse .phi.1, shown in FIG. 3(B) is applied to the other terminals of the capacitors in the even stages.
In this charge pump circuit, a high voltage, for example, 20 volts is obtained at the output terminal VO by sequentially repeating the operation such that the charge stored in the capacitor C1 through the load MOSFET QR from the power source VC is transferred to the next capacitor C2 through the MOSFET Q1 by applying the clocks .phi.1, .phi.2 as shown in FIG. 3 and the charge of this capacitor C2 is transferred to the next capacitor C3 through the MOSFET Q2.
When such a charge pump circuit is rewritten by applying a high voltage to a selected row of a memory cell array in combination with an address decoder, the following problem arises. There is no trouble in the supply of the high voltage, thus stepped-up, to the control gate of the row selected because the output of the address decoder becomes high. As the charge pump circuit in FIG. 2 utilizes the charge stored in the capacitor, the current supplying ability of the capacitor is extremely low. When the outputs of the address decoders are at a low level in the remaining rows not selected, the current from this charge pump circuit must not flow out through the output stage. If the above-described current flowout occurs in the rows not selected, a sufficient high voltage cannot be applied to the row thus selected.